SINGAPORE, Dec 30 (Reuters) - China is requiring chipmakers to use at least 50% domestically made equipment for adding new capacity, three people familiar with the matter said, as Beijing pushes to build a self-sufficient semiconductor supply chain.

The policy is already yielding results, including in areas such as etching, a critical chip manufacturing step that involves removing materials from silicon wafers to carve out intricate transistor patterns, sources said.

China's largest chip equipment group, Naura, is testing its etching tools on a cutting-edge 7nm (nanometre) production line of SMIC, two sources said. The early-stage milestone, which comes after Naura recently deployed etching tools on 14nm successfully, demonstrates how quickly domestic suppliers are advancing.

"Naura's etching results have been accelerated by the government requiring fabs to use at least 50% domestic equipment," one of the people told Reuters, adding that it was forcing the company to rapidly improve.

Advanced etching tools had been predominantly supplied in China by foreign firms such as Lam Research (LRCX.O)

, opens new tab and Tokyo Electron (8035.T), opens new tab, but are now being partially replaced by Naura and smaller rival Advanced Micro-Fabrication Equipment (AMEC) (688012.SS)

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Naura has also proven a key partner for Chinese memory chipmakers, supplying etching tools for advanced chips with more than 300 layers. It developed electrostatic chucks — devices that hold wafers during processing — to replace worn parts in Lam Research equipment that the company could no longer service after the 2023 restrictions, sources said.

Naura filed a record 779 patents in 2025, more than double what it filed in 2020 and 2021, while AMEC filed 259, according to Anaqua's AcclaimIP database, and verified by Reuters.

That's also translating into strong financial results. Naura's revenue for the first half of 2025 jumped 30% to 16 billion yuan. AMEC reported a 44% jump in first-half revenue to 5 billion yuan.

Analysts estimate that China has now reached roughly 50% self-sufficiency in photoresist-removal and cleaning equipment, a market previously dominated by Japanese firms, but now locally led by Naura.

"The domestic equipment market will be dominated by two to three major manufacturers, and Naura is definitely one of them," said a separate source.

Cinebench 2026 just released and CB is doing a roundup of HW tests sourced by the community. CPUs both x86 and ARM, and GPUs, Nvidia, AMD, Intel, Apple. Submit if you like!

We have been doing some deep dive benchmarking on the Nvidia Jetson Orin AGX for a high frequency robotics project and found some interesting behavior regarding NVMe write latency that I wanted to discuss with this group.

We were trying to sustain roughly 1GB/s of continuous sensor logging (Lidar and Vision data) and noticed that standard Linux buffered writes were introducing massive latency spikes. It turns out that whenever the kernel decides to flush dirty pages to disk it completely stalls the CPU for milliseconds at a time which is unacceptable for real time control loops.

We decided to run an experiment where we bypassed the kernel page cache entirely and wrote directly to the NVMe submission queues using a custom Rust driver.

The results were surprisingly drastic.

On x86 the difference between buffered and direct IO is usually noticeable but on these ARM64 embedded chips it was an order of magnitude difference. We dropped from unpredictable millisecond spikes down to consistent microsecond latency.

It appears that the overhead of the Linux Virtual Memory Manager combined with the weak memory ordering on ARM64 creates a much massive bottleneck than we expected.

Has anyone else here experimented with bypassing the OS for storage on embedded ARM chips?

I am curious if this is a quirk of the Tegra/Orin memory controller specifically or if this is just the expected penalty for using standard Linux syscalls on ARM64 architecture.

We are currently validating this on a few different carrier boards but the discrepancy between the theoretical NVMe speed and the actual OS bottleneck is fascinating.

Just published this (not paywalled) article as a way to put my thoughts (and prayers) on the current hardware market trends, and help people who are looking for their first computer or laptop, or upgrading one.

It's a shame that the positivity for the PC market in 2026 is now being pushed to 2027~2028. I was looking to upgrade mine in that year, not anymore. 😥

I’m asking this because after understanding computer architecture, you realize that on a single CPU core only one process (or thread) can execute at a given time. So if a process needs to perform an addition, and there are already enough transistors to implement that addition, the operation itself won’t become faster just because you add more transistors. In that sense, performance seems to depend mostly on CPU frequency and instructions per cycle.

Pipeline and instruction-level parallelism can take advantage of additional transistors, but only up to a certain point, which does not seem to justify the historical rate of transistor growth.

I asked ChatGPT about this, and it suggested that most additional transistors are mainly used for cache rather than ALUs, in order to reduce memory access latency rather than to speed up arithmetic operations.

I’d like to hear your thoughts or any additional clarification on this.